1. Field of the Invention
The present invention relates to an image pickup system for transmitting a video signal including a synchronous signal from a device on the transmission side to a device on the reception side and reproducing the video signal on the reception side and, more particularly, to a synchronous signal generator for generating a synchronous signal on the transmission side and a synchronizing circuit for synchronizing the operation on the transmission side with the synchronous signal.
2. Description of the Related Art
In the case of constituting an image pickup system by a plurality of TV cameras as a monitor system by monitor cameras, it is required to synchronize the operations of the TV cameras with each other in order to enable the synchronous processing of a plurality of images. The timings for the operations of the respective cameras are generally set on the basis of the reference clocks from oscillators which are provided in the respective TV cameras. The TV cameras are operated at their own timings unless they are caused to agree with each other in advance. In order to synchronize the operations of the TV cameras, a synchronous signal common to these cameras is conventionally provided in a conventional image pick up system.
FIG. 1 shows the waveform of a composite synchronous signal CSY for obtaining the timing for the operation of a TV camera of an NTSC system.
The composite synchronous signal CSY is input to a TV camera from an external circuit and includes a horizontal synchronous signal HSY, a vertical synchronous signal VSY and an equivalent pulse EQP. These horizontal synchronous signal HSY, vertical synchronous signal VSY and equivalent pulse EQP are arranged in a predetermined order in time series. The horizontal synchronous signal HSY and the vertical synchronous signal VSY are separated from the composite synchronous signal CSY by a differentiator and an integrator. That is, the horizontal synchronous signal HSY is obtained by differentiating the composite synchronous signal CSY to detect the trailing edge of the signal and the vertical synchronous signal VSY is obtained from a change in the integrated value of composite synchronous signal CSY.
FIG. 2 is a block diagram of the structure of a synchronizing circuit for obtaining the horizontal synchronous signal HSY and the vertical synchronous signal VSY from the composite synchronous signal CSY.
A hybrid signal HYB input from an external circuit is separated into a video signal VDO for a video component and a composite synchronous signal CSY for a synchronous component by a synchronous signal separator 1, and the composite synchronous signal CSY is further input to a vertical/horizontal separator 2. The vertical/horizontal separator 2 detects the trailing edge of the signal by differentiating the composite synchronous signal CSY, thereby obtaining a horizontal synchronous signal HSY.sub.0 and integrates the composite synchronous signal CSY and obtains a vertical synchronous signal VSY from a change in the integrated value.
A voltage-controlled oscillator (VCO) 3 generates a reference clock MCK in accordance with the output PDO of a later-described phase comparator 4. A counter 5 counts the reference clocks MCK. The counter is reset by the vertical synchronous signal VSY and outputs the count value to a decoder 6. The decoder 6 generates the horizontal synchronous signal HSY from the count value of the counter 5. The horizontal synchronous signal HSY is input to the phase comparator 4 together with the horizontal synchronous signal HSY.sub.0 output from the vertical/horizontal separator 2. The phase comparator 4 compares the phases of the horizontal synchronous signal HSY.sub.0 and the horizontal synchronous signal HSY and supplies the output PDO to the VCO 3, thereby constituting a PLL (Phase Locked Loop). In this way, the horizontal synchronous signal HSY is synchronized with the horizontal synchronous signal HSY.sub.0 which is separated from the composite synchronous signal CSY.
In an image pickup system using a plurality of TV cameras, the hybrid signal HYB including a synchronous component is output from a reference TV camera and input to the respective TV cameras. In the reference camera for generating the hybrid signal HYB, a TV synchronous signal having a predetermined format is generated in the TV camera, and the scanning timing for an image sensor is set on the basis of the synchronous signal. A driving circuit for driving the image sensor of the TV camera is composed of a circuit of a synchronizing system for generating synchronous signals and a circuit of a driving system for generating an image sensor driving clock. These circuits are composed of one chip as a single integrated circuit.
However, when these circuits are composed of one chip, there are problems of beat noise generated by the difference in oscillators and the periodical noise generated by the operation of the counter provided in the circuit of the synchronizing system. Although the beat noise can be eliminated by using an oscillator in common to both circuits, it is impossible to eliminate the periodical noise because the operation of the counter itself causes the power source noise.
FIG. 3 is a block diagram of the structure of a conventional circuit of a synchronizing system. A binary counter 11 counts reference clocks CLK and operates with a horizontal scanning period H. When the count value of the counter 11 reaches a predetermined value, the output of a decoder 12 resets the binary counter 11. A second binary counter 13 counts the reference clock CLK and it is reset by the output of the decoder 12 in the same way as the binary counter 11. The output of the counter 13 is input to a decoder 14. The decoder 14 generates various synchronous signals having a period of 1H which are represented by a horizontal scanning signal HD.
If each of the binary counters 11 and 13 has a 4-bit structure, it is composed of four flip-flops, as shown in FIG. 4. In this case, the count value and the number of turning points vary as shown in the following table.
______________________________________ Count value Number of turning points ______________________________________ 0000 -- 0001 1 0010 2 0011 1 0100 3 0101 1 0110 2 0111 1 1000 4 . . . . . . ______________________________________
In the binary counters 11 and 13, each of which is composed of a multi-stage flip-flop corresponding to the number of bits, since the amount of current flowing to the counters varies in accordance with the number of edges (leading edges or trailing edges), power source noise is caused in correspondence with the periodicity of the number of edges. Noise having a period of 1H is therefore produced on the driving clock and superimposed on the video output from the image sensor. The noise appears as vertical fringes on the reproduced picture.
As a countermeasure, use of a polynomial counter such as that shown in FIG. 5 is proposed.
A polynomial counter having a 4-bit structure is composed of four flip-flops 15a to 15d connected in series and a common clock CLK is supplied to the four flip-flops 15a to 15d. The exclusive OR 16 of the output of the flip-flop at the first stage and the output of the flip-flop at the fourth stage is input to the first stage and the outputs of the four flip-flops 15a to 15d are combined with each other. Since the number of the edges is not increased or reduced rapidly, the periodic noise is reduced.
In the polynomial counter, however, the number of the edges itself also increases or reduces in the range of 1 to the number of bits. For example, in an NTSC system, since the clock frequency is 14.32 MHz and it is necessary to count 910 clocks during 1H, the counter has a 10-bit structure and the number of the edges increases or reduces in the range of 1 to 10. For this reason, although the vertical fringes are not remarkable in comparison with the case using the binary counters 1 and 3, wide blur vertical fringes disadvantageously appear.
In the synchronizing circuit on the side of receiving the hybrid signal HYB, since analog circuits such as the differentiator and the integrator are mainly used in order to obtain the horizontal synchronous signal HSY and the vertical synchronous signal VSY by separating them from the composite synchronous signal CSY, it is necessary to take the delays of these analog circuits into adequate consideration. However, since the delays of these analog circuits are dependent on a temperature, it is very difficult to determine various parameters with due consideration for the delays.
In obtaining the horizontal synchronous signal HSY, in order to discriminate the equivalent pulse EQP having a period equivalent to 1/2 of the period of the horizontal synchronous signal HSY, a strobe pulse is set by using a counter which operates with the horizontal scanning period H in accordance with the trailing edge of the composite synchronous signal CSY, thereby eliminating the equivalent pulse EQP. However, since the counter which operates during the horizontal scanning causes beat noise, the periodical noise is superimposed on the video signal and vertical fringes are produced on the reproduced picture.
If the oscillation range of the VCO 3 is narrow, the time required for the PLL to be locked, in other words, the time required for the horizontal synchronous signal HSY to be synchronous with the horizontal synchronous signal HSY.sub.0 is long, which sometimes delays the rise time of the apparatus.